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Publications: [DBLP] [Google Scholar]

  Journal Publications:
  1. Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao. Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM, IEEE Transactions on Reliability (TR), 2016, 65(4): 1755-1768.
  2. Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao. Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2016, 24(11): 3310-3322.
  3. Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li. Spintronic Memristor as Interface Between DNA and Solid State Devices, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2016, 6(2): 212-221.
  4. Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li. Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016, 35(3): 380-393.
  5. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2015, 23(11): 2617-2628.
  6. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: An Efficient Simulator for Static Power Grid Analysis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2014, 22(10): 2103-2116.
  7. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi. Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2014, 22(4): 899-912.
  Conference/Workshop Publications:
  1. Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu. Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers, 26th edition on Great Lakes Symposium on VLSI (GLSVLSI 2016): 133-136, Boston, 2016.
  2. Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie. ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY, 35th International Conference on Computer-Aided Design (ICCAD 2016): 118, Austin, 2016.
  3. Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li. A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016): 110-115, Pittsburgh, 2016.
  4. You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao. A novel circuit design of true random number generator using magnetic tunnel junction, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016): 123-128, Beijing, 2016.
  5. Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li. An overview on memristor crossabr based neuromorphic circuit and architecture, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2015): 52-56, Daejeon, 2015.
  6. Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia. A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback, ACM Great Lakes Symposium on VLSI (GLSVLSI 2015): 69-74, Pittsburgh, 2015. (Best Paper Nomination)
  7. Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai. Early Stage Real-Time SoC Power Estimation Using RTL Instrumentation, 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015): 779-784, Chiba/Tokyo, 2015.
  8. Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou. Power Supply Noise Aware Evaluation Framework for Side Channel Attacks and Countermeasures, International Conference on Field-Programmable Technology (FPT 2014): 161-166, Shanghai, 2014, (Invited Paper by Special Session of Hardware Security).
  9. Wei Zhao, Yici Cai, Jianlei Yang. Fast Vectorless Power Grid Verification using Maximum Voltage Drop Location Estimation, 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014): 861-866, Singapore, 2014.
  10. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. Selected Inversion for Vectorless Power Grid Verification by Exploiting Locality, IEEE International Conference on Computer Design (ICCD 2013): 257-263, Asheville, 2013. (Best Paper Award)
  11. Wei Zhao, Yici Cai, Jianlei Yang. A Multilevel H-matrix-based Approximate Matrix Inversion Algorithm for Vectorless Power Grid Verification, 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013): 163-168, Yokohama, 2013.
  12. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: Efficient Transient Simulation for Power Grid Analysis, IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2012): 653-659, San Jose, 2012, (Invited Paper by Special Session of Power grid simulation and verification for billion-transistor VLSI designs).
  13. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: A Linear Simulator for Power Grid, IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2012), Taipei, 2012. (Invited Paper).
  14. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi. Fast Poisson Solver Preconditioned Method for Robust Power Grid Analysis, IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011): 531-536, San Jose, 2011.
  15. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: A Linear Simulator for Power Grid, IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011): 482-487, San Jose, 2011, (Invited Paper by Special Session of 2011 TAU Power Grid Contest).
  16. Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze. Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization, ACM Great Lakes Symposium on VLSI (GLSVLSI 2015): 199-204, Lausanne, 2011.